A/D converters are used for converting an analog input signal into a digital output signal. The A/D conversion is normally performed by comparing an unknown analog signal with a known reference value. For the A/D conversion, there are a series of different conversion methods in which either the analog signal is amplified, i.e. is multiplied by a prescribed weighting factor, or the reference signal is divided, i.e. is divided by a prescribed weighting factor.
FIG. 1 shows a three-stage pipeline converter with the stages A, B, C. Pipeline converters likewise compare the analog signal ain with the reference value, but the unknown analog signal ain is normally amplified two-fold and compared with a constant reference variable REF. The three-stage pipeline converter shown comprises a sample & hold stage S/HA which is used to sample and hold the analog input signal ain. In addition, each of the three stages A-C comprises an amplifier VA (or a weighting unit) with a weighting or gain factor k=2, and a comparator KA which is used to compare the digitally converted analog input signal ain with a reference value REF. If the digitally converted analog signal ain is greater than the reference value REF, the reference value REF is deducted from the two-fold amplified analog signal ain at a subtraction node S, and the resultant difference value is moved on to the sample & hold stage S/HB in the next converter stage B. If, on the other hand, the analog signal ain is less than the prescribed reference value, the two-fold amplified analog signal ain VA is immediately moved on to the sample & hold stage S/HB in the converter stage B.
In the first case, the converter stage A generates a logic “1” digital value, and in the latter case it generates a logic “0” digital value. In this way, each of the stages A-C generates one bit (D/b) which together produce a digital, binary code which may be between 0 and 2n−1, where n is the number of converter stages. In this case, the bit weight of the digital conversion result is equal to 2 on account of the weighting or gain factor 2 of the amplifiers V.
While a successive approximation converter requires n cycles before the conversion result is definite, and only then is it possible to start a new conversion again, the conversion result in the pipeline converter as shown in FIG. 1 is admittedly also not valid until after n cycles, but the next analog value to be converted can be moved into the pipeline after just the first cycle in stage A.
The accuracy of the two converter types is definitively determined by the accuracy of the division or multiplication factor k=2 which is used to multiply or divide the analog signal or the reference value. When weighting with a numeric base of two, the accuracy of the factor 2, which arises in the division factor ½, ¼, ⅛ etc. in the case of the SA converter and in the multiplication factor 2 in the case of the pipeline converter, is of particular importance. An error in one of these weighting factors has an immediate effect on the digital end results, as the following example shows:
A DA converter with a resolution of 8 bits is capable of quantizing an unknown analog signal or a reference variable into 28=255 levels. The A/D converter now has an analog signal applied to it which corresponds to a quantization level with the decimal value 128. This analog value is now compared with a reference value which has been generated by dividing a prescribed reference variable (the prescribed reference variable is multiplied by a factor of ⅜, for example). With correct division, this would result in a reference value which corresponds to a quantization level of 127, for example, and which is less than the analog value 128. On account of an inaccuracy in the division factor (⅜), however, the comparison with the reference value which corresponds to a decimal value of 128 and 129 also gives the result that the analog value is greater than the reference value. Since the reference value for the quantization levels is incorrectly less than the analog value, the result which is output for the comparison is a “1” instead of a “0”.
Besides the inaccuracy in the weightings carried out by the converters (division, multiplication), the accuracy of the A/D converters is affected by transient signal voltages. The inputs and outputs of the amplifiers V, of the comparators K and of the subtraction nodes S normally have transient signals applied to them which have overshoots, for example, and decay to a constant value only after a particular decay time.
In an n-bit converter, n decisions need to be made in order to obtain a digital n-bit word, each of these decisions needing to be at least as accurate as a quantization level in the final digital conversion result. The speed at which comparisons and other operations can be performed in an n-bit converter is determined by the dynamic response of the signals to be processed in the converter. In the case of an SA converter, a relatively large amount of time is needed in order to generate the necessary reference values with the desired accuracy using the digital controller and the DA converter. In the case of the pipeline converter shown in FIG. 1, some time is needed before the amplifiers V have reached a steady state. If the operations performed by the A/D converter are performed too early, errors may therefore arise.
In order to reduce the frequency of error and hence to increase the accuracy of the A/D converters, it is already known practice to use A/D converters with redundant code. A/D converters with redundant code are distinguished in that a reference value, such as ¾ of a prescribed reference variable, with which the unknown analog signal is compared does not form the limit of the value range for a subsequent comparison, but rather, depending on the result of the comparison, a smaller or larger value is used. This will be explained in more detail below using an example.
An 8-bit converter quantizing an analog signal into values of between 0 and 255 has an analog signal supplied to it whose analog value corresponds to a decimal, quantized value of 128. In a comparison in stage n, this analog value is compared with a reference value which corresponds to a quantization level with the decimal value 127. This establishes that the reference value is less than the analog value. So as now to avoid errors on account of inaccurate weighting or transient signal fluctuations, the next comparison, performed by the A/D converter, does not involve selection of the value range between 127 and 255, as usual, but rather involves selection of a value range between a smaller value, e.g. 120, and 255. This means that minor incorrect decisions can still be corrected later and do not affect the final conversion result.
In a conventional, binary converter, on the other hand, once a bit has been set incorrectly it cannot be corrected again in the subsequent conversion steps.
The error-preventing property of redundant A/D converters is achieved by virtue of the weighting factors, such as the gain factor VK of the amplifiers V or the division factor which the digital controller (weighting unit 4) uses to generate a reference value from a prescribed reference variable, are not based on a numeric base of 2, but rather are based on a smaller numeric base e.g. 1.8.
In an SA converter with redundant code, the reference elements used to divide the prescribed reference variable are then not twice as large, four times as large etc. (reference elements may be capacitors, current sources, resistors etc.), but rather are less than twice as large, four times as large etc. The reference elements may give rise, by way of example, to a bit weight for the digital output signal of 1; 1.8; 1.82; 1.83 etc. In the case of a pipeline converter as shown in FIG. 1, this means that the weighting or gain factor of the amplifiers would not need to be two but rather 1.8.
The difficulty with such redundant A/D converters is that the factor 1.8 cannot be generated as easily as the factor 2 by respectively doubling the reference element. As a result, errors are obtained which are already larger in principal than in a binary converter.
Each of the converter stages A, B, C delivers one bit digA, digB, digc of the digital conversion result as the result of the comparison performed by the stages. In the example shown in FIG. 1, a redundant code 1,0,0,0 is obtained. However, the digital conversion result is not binary, with a bit weight of 2, and therefore also does not correspond to the decimal number 23=8, but rather is based on the base of 1.8 and thus corresponds to the number 1.83=5.832. This result is calculated as 0·1+0·1.81+0·1.82+1·1.83=5.832. The individual bits of the conversion result are added using the arrangement shown at the bottom in FIG. 1, which, for this purpose, has memories for storing multiplication factors MF, multiplying a plurality of storage elements SG and addition nodes AK. Finally, the code with a bit weight of 1.8 is used to generate a binary code. After the last addition node AKc (bottom far right), the binary code associated with the redundant code is obtained, that is to say the conversion result in binary form.
Errors in the binary conversion result arise particularly when the weightings Vi for the analog signal or for the reference variable which are performed by the A/D converter does not correspond precisely to the stored multiplication factors, which is used when converting the redundant code into a binary code.
To date, attempts have been made to compensate for this error by altering the gains V1 for the pipeline converter shown in FIG. 1 in the converter analog circuit. This is relatively complicated, however.
Hence, German Laid-Open Specification DE 101 33 538.5 A1 has proposed an A/D converter in which it is a simple matter to calibrate the multiplication factors MFi.
This A/D converter based on the prior art, which is shown in FIG. 2, weights not only the analog signal to be converted or a reference variable but also an auxiliary signal PSR (Pseudo Random) in the A/D converter and at the same time has a calibration amplifier for weighting digital random signal PSR, whose gain factor can be altered. The weighting factor G applied by the A/D converter is ascertained by virtue of the random signal PSR weighted by the A/D converter and the auxiliary signal PSR (or signals derived therefrom) weighted by the controllable calibration amplifier and also the original (unweighted) random signal being supplied to an evaluation unit which performs correlation analysis.
FIG. 2 shows a converter stage A in a conventional pipeline converter with an associated calibration device KAL. The pipeline converter is an A/D converter with redundant code and comprises, in the normal way, an amplifier V with a weighting factor 2, a comparator K and a subtraction node S.
Next to the first converter stage A, FIG. 2 also shows a second converter stage B and a third converter stage C.
The sum of the PSR signal and the input signal is finally amplified by an amplifier VA, e.g. a factor VA=2. The analog summed signal is also compared with a reference variable REF at the comparator. If the analog summed signal is greater than the reference variable REF, the reference variable is deducted from the two-fold amplified summed signal, and the resultant value is output to the next converter stage B. Otherwise, the two-fold amplified analog summed signal, comprising the analog input signal ain and the digital random signal, is forwarded to the next converter stage B immediately without subtracting the reference signal.
The calibrating device KAL comprises a controllable digital weighting unit or calibration amplifier and an evaluation unit.
The digital signal element generated in the pipeline converter is tapped off at the output of the converter stage B and is likewise supplied to the evaluation unit. The evaluation unit comprises a subtraction node SUB which is used to subtract the digital random signal PSR multiplied by the weighting factor G in the controllable digital weighting unit from the digitally converted analog signal. If the weighting factor GA in the controllable weighting unit and the gain factor VA in the amplifier match, the resultant difference signal DIF comprises only the uncorrelated quantization error plus the input signal. If the weighting factor and the gain VA do not match, a remainder of the digital random signal is also left over.
The difference signal DIF can be evaluated using a correlation unit Rxy, the correlation unit performing cross-correlation of the difference signal DIF with the original, digital random signal PSR. The result of the correlation is used to adjust the weighting factor GA in the controllable weighting unit G until the difference signal DIF no longer contains any remainder of the digital random signal.
In this case, the output of the correlation unit Rxy is connected to the weighting unit via a low-pass filter TP, for example.
FIG. 3 shows a circuit implementation for a converter-stage in the pipeline analog/digital converter based on the prior art.
FIG. 3 shows a single-ended implementation for a two-bit digital/analog converter having four DAC capacitors C1 to C4. The DAC has a reference signal REF, a thermometer-coded comparator output signal and a sample control signal applied to it. During the sample phase, the analogue input signal ain is applied to the DAC capacitors C1 to C4. The converter stage also comprises a feedback operational amplifier having a feedback capacitor.
The pipeline analog/digital converter based on the prior art which is shown in FIG. 2 has the following drawbacks.
To feed the digital random signal to the analog/digital converter's signal path formed by the converter stages, an additional calibration digital/analog converter is necessary. This increases the circuit complexity for the analog/digital converter.
The converter stage based on the prior art which is shown in FIG. 3 comprises various DAC capacitors C1, C2, C3 and C4 which result in different DAC stages on account of production variations and manufacturing tolerances. To transfer from one DAC stage in the digital/analog converter to another DAC stage, a transfer error or DAC error is therefore obtained. This transfer error in the digital/analog converter is fed into the signal path and continues through the converter stages, so that the digital output value from the overall analog/digital converter is corrupted.
It is therefore the object of the present invention to provide an analog/digital converter in which the result corruptions on account of a transfer error are minimal.